US 12,471,371 B2
Array substrate and manufacturing method therefor, electronic paper display apparatus and driving method therefor
Gang Hua, Beijing (CN); Chao Tian, Beijing (CN); Min Wang, Beijing (CN); Dong Wang, Beijing (CN); Zhe Wang, Beijing (CN); Shaobo Li, Beijing (CN); Pengkai Fan, Beijing (CN); Jintang Hu, Beijing (CN); and Meng Gong, Beijing (CN)
Assigned to BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Beijing (CN); and BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD., Beijing (CN)
Appl. No. 17/770,020
Filed by BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Beijing (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Apr. 14, 2021, PCT No. PCT/CN2021/087164
§ 371(c)(1), (2) Date Apr. 18, 2022,
PCT Pub. No. WO2021/233022, PCT Pub. Date Nov. 25, 2021.
Claims priority of application No. 202010435839.3 (CN), filed on May 21, 2020.
Prior Publication US 2022/0399382 A1, Dec. 15, 2022
Int. Cl. H10D 86/60 (2025.01); G02F 1/16766 (2019.01); G02F 1/1685 (2019.01); H10D 86/01 (2025.01); H10D 86/40 (2025.01)
CPC H10D 86/60 (2025.01) [G02F 1/16766 (2019.01); G02F 1/1685 (2019.01); H10D 86/0221 (2025.01); H10D 86/441 (2025.01)] 12 Claims
OG exemplary drawing
 
1. An array substrate having a plurality of sub-pixel regions, the array substrate comprising:
a substrate;
a first transistor and a second transistor that are disposed on a side of the substrate and located in each sub-pixel region;
a first pixel electrode and a second pixel electrode that are disposed on the side of the substrate and located in the sub-pixel region, the first pixel electrode being disposed on a side of the second pixel electrode away from the substrate;
a plurality of data lines extending in a first direction;
a third transistor disposed on the side of the substrate and located in the sub-pixel region, one of a source and a drain of the third transistor being electrically connected to the second pixel electrode; and
a plurality of common electrode lines extending in a second direction, and another of the source and the drain of the third transistor being electrically connected to a common electrode line of the plurality of common electrode lines, the second direction crossing the first direction, wherein
the first pixel electrode and the second pixel electrode are insulated from each other; the first pixel electrode is electrically connected to the first transistor, and the second pixel electrode is electrically connected to the second transistor;
an orthographic projection of the first pixel electrode on the substrate partially overlaps with an orthographic projection of the second pixel electrode on the substrate; or an orthographic projection of the first pixel electrode on the substrate does not overlap with an orthographic projection of the second pixel electrode on the substrate, and partial boundaries of the orthographic projection of the first pixel electrode on the substrate and the orthographic projection of the second pixel electrode on the substrate are tangential;
one of a source and a drain of the first transistor is electrically connected to the first pixel electrode, and another of the source and the drain of the first transistor is electrically connected to a data line of the plurality of data lines; and one of a source and a drain of the second transistor is electrically connected to the first pixel electrode or the data line, and another of the source and the drain of the second transistor is electrically connected to the second pixel electrode.