US 12,471,364 B2
Hybrid stacked field effect transistors
Ruilong Xie, Niskayuna, NY (US); Bahman Hekmatshoartabari, White Plains, NY (US); Alexander Reznicek, Troy, NY (US); and Heng Wu, Guilderland, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Sep. 22, 2021, as Appl. No. 17/481,504.
Prior Publication US 2023/0085628 A1, Mar. 23, 2023
Int. Cl. H10D 84/85 (2025.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 84/856 (2025.01) [H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6733 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 84/017 (2025.01); H10D 84/0172 (2025.01); H10D 84/0186 (2025.01); H10D 84/0188 (2025.01); H10D 84/038 (2025.01)] 11 Claims
OG exemplary drawing
 
1. A method of fabricating a hybrid stacked semiconductor device, the method comprising:
forming a nanosheet stack on a substrate, the nanosheet stack comprising a first stack portion including first channels, a second stack portion stacked on the first stack portion, the second stack portion including second channels, and a dielectric spacer interposed between the first stack portion and the second stack portion;
forming an all-around gate including a first gate portion that wraps around the first channels and a second gate portion that wraps around the second channels;
forming a first gate extension on a first side of the nanosheet stack to contact the first gate portion;
forming a second gate extension on a second side of the nanosheet stack to contact the second gate portion, the second side being different from the first side;
removing portions of the first and second gate extensions from an active region of the substrate;
removing a portion of the nanosheet stack from the active area to expose a portion of the substrate;
forming a first source/drain directly on the exposed portion of the substrate, the first source/drain contacting the first channels included in the first stack portion of the nanosheet stack;
covering the first source/drain with an isolation dielectric;
forming a second source/drain on the isolation dielectric, the second source/drain contacting the second channels included in the second stack portion of the nanosheet stack;
forming a first gate contact that contacts the first gate extension to establish conductivity with the first gate portion; and
forming a second gate contact that contacts the second gate extension to establish conductivity with the second gate portion.