US 12,471,362 B2
Integrated circuit structures having ultra-high conductivity global routing
Abhishek Anil Sharma, Portland, OR (US); Tahir Ghani, Portland, OR (US); Anand S. Murthy, Portland, OR (US); Sagar Suthram, Portland, OR (US); Pushkar Ranade, San Jose, CA (US); Wilfred Gomes, Portland, OR (US); Rishabh Mehandru, Portland, OR (US); and Cory Weber, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 30, 2022, as Appl. No. 17/855,598.
Prior Publication US 2024/0006416 A1, Jan. 4, 2024
Int. Cl. H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01); H10D 30/62 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 84/85 (2025.01)
CPC H10D 84/853 (2025.01) [H10D 30/6211 (2025.01); H10D 30/6713 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a device layer having a plurality of transistors; and
a plurality of metallization layers above the plurality of transistors of the device layer, wherein one or more of the metal layers comprises a material having a critical temperature greater than 10 Kelvin and less than 300 Kelvin.