US 12,471,358 B2
Semiconductor structure and method of manufacturing the same
Yuan-Sheng Huang, Taichung (TW); and Ryan Chia-Jen Chen, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on May 22, 2024, as Appl. No. 18/670,753.
Application 18/670,753 is a continuation of application No. 17/814,858, filed on Jul. 26, 2022, granted, now 12,020,986.
Application 17/814,858 is a continuation of application No. 17/008,098, filed on Aug. 31, 2020, granted, now 11,404,321, issued on Aug. 2, 2022.
Prior Publication US 2024/0312842 A1, Sep. 19, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/76 (2006.01); H01L 29/94 (2006.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01)
CPC H10D 84/038 (2025.01) [H10D 62/115 (2025.01); H10D 64/017 (2025.01); H10D 84/0158 (2025.01); H10D 84/834 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving a substrate;
depositing a first gate layer over the substrate;
patterning the first gate layer to form a first gate stack and leaving at least one void exposed from a sidewall of the first gate stack;
depositing a dielectric layer on the sidewall of the first gate stack; and
removing a first portion of the dielectric layer from the sidewall of the first gate stack while leaving a second portion of the dielectric layer to fill the at least one void.