US 12,471,357 B2
Semiconductor device and method
Ching-Feng Fu, Taichung (TW); Yu-Lien Huang, Jhubei (TW); Tsai-Jung Ho, Xihu Township (TW); and Huan-Just Lin, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jun. 29, 2023, as Appl. No. 18/344,441.
Application 18/344,441 is a continuation of application No. 17/232,374, filed on Apr. 16, 2021, granted, now 11,728,218.
Prior Publication US 2023/0352344 A1, Nov. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 84/03 (2025.01); H10D 30/01 (2025.01); H10D 84/01 (2025.01); H10D 84/85 (2025.01)
CPC H10D 84/038 (2025.01) [H10D 30/024 (2025.01); H10D 84/013 (2025.01); H10D 84/0158 (2025.01); H10D 84/853 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a plurality of fins protruding from a substrate;
forming a plurality of source/drain regions on the plurality of fins;
depositing an inter-layer dielectric (ILD) layer over the plurality of source/drain regions;
depositing a sacrificial material over the ILD layer;
patterning a plurality of openings in the sacrificial material;
depositing a mask material within the plurality of openings;
after depositing the mask material, removing the sacrificial material; and
etching the ILD layer using the remaining mask material as an etching mask to expose the plurality of source/drain regions.