US 12,471,356 B2
Stepped isolation regions
Hui Hung Kuo, Kaohsiung (TW); Hsin Fu Lin, Hsinchu (TW); and Hsin Heng Wang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Feb. 16, 2023, as Appl. No. 18/169,928.
Prior Publication US 2024/0282636 A1, Aug. 22, 2024
Int. Cl. H01L 29/76 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 21/56 (2006.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 84/038 (2025.01) [H01L 21/02617 (2013.01); H01L 21/31144 (2013.01); H01L 21/3213 (2013.01); H01L 21/56 (2013.01); H10D 62/115 (2025.01); H10D 84/0151 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method for fabricating a semiconductor structure, comprising:
forming mask segments over a semiconductor material;
etching the semiconductor material to form first trenches, wherein the first trenches have a first trench maximum width and a first trench depth;
forming a coating in the first trenches, wherein the coating has a coating depth less than the first trench depth, and wherein uncovered portions of the semiconductor material extend from the coating to the mask segments;
performing an etch process to etch the mask segments and the uncovered portions of the semiconductor material to form second trenches over the first trenches, wherein the second trenches have a second minimum width greater than the first trench maximum width and a second trench depth less than the first trench depth; and
removing the coating from the first trenches.