US 12,471,353 B2
Gate-all around transistor with isolating feature under source/drain
Yu-Xuan Huang, Hsinchu (TW); Ching-Wei Tsai, Hsinchu (TW); Hou-Yu Chen, Zhubei (TW); and Kuan-Lun Cheng, Hsin-chu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 28, 2024, as Appl. No. 18/759,037.
Application 18/759,037 is a continuation of application No. 17/870,451, filed on Jul. 21, 2022, granted, now 12,040,403.
Application 17/870,451 is a continuation of application No. 17/082,711, filed on Oct. 28, 2020, granted, now 11,444,200, issued on Sep. 13, 2022.
Claims priority of provisional application 62/953,715, filed on Dec. 26, 2019.
Prior Publication US 2024/0355928 A1, Oct. 24, 2024
Int. Cl. H10D 84/01 (2025.01); H10D 62/10 (2025.01); H10D 84/03 (2025.01)
CPC H10D 84/0158 (2025.01) [H10D 62/119 (2025.01); H10D 84/038 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
semiconductor material layers stacked above a substrate along a first direction;
a gate structure wrapping around the semiconductor material layers;
an epitaxial structure coupled to the semiconductor material layers in a second direction that is different from the first direction; and
a SiGe-containing layer located below the epitaxial structure, wherein:
a material of the SiGe-containing layer is different from a material of the epitaxial structure,
the SiGe-containing layer comprises a first portion with a first thickness in the first direction, and a second portion with a second thickness in the first direction, and the second thickness is smaller than the first thickness, and
the SiGe-containing layer is partially sandwiched between the epitaxial structure and the gate structure in the second direction.