US 12,471,351 B2
Shielded gate trench power MOSFET with high-k shield dielectric
Zia Hossain, Tempe, AZ (US); Balaji Padmanabhan, Chandler, AZ (US); Christopher Lawrence Rexer, Scottsdale, AZ (US); Gordon M. Grivna, Mesa, AZ (US); and Sauvik Chowdhury, San Jose, CA (US)
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed by SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Phoenix, AZ (US)
Filed on Feb. 9, 2022, as Appl. No. 17/650,456.
Prior Publication US 2023/0253468 A1, Aug. 10, 2023
Int. Cl. H10D 64/00 (2025.01); H10D 30/01 (2025.01); H10D 30/66 (2025.01); H10D 64/27 (2025.01)
CPC H10D 64/513 (2025.01) [H10D 30/0297 (2025.01); H10D 30/665 (2025.01); H10D 30/668 (2025.01); H10D 64/118 (2025.01)] 23 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a substrate having a semiconductor region;
a trench defined in the semiconductor region and having a sidewall;
a shield electrode disposed in the trench and insulated from the sidewall of the trench by a shield dielectric, the shield dielectric having a low-k dielectric portion and a high-k dielectric portion;
a gate electrode disposed in the trench and at least partially surrounded by a gate dielectric; and
an inter-electrode dielectric disposed between the shield electrode and the gate electrode, the high-k dielectric portion being insulated from the sidewall by at least a portion of the low-k dielectric portion, the high-k dielectric portion being in contact with the shield electrode.