US 12,471,350 B2
Semiconductor structure and method of forming the same
Chia-Hao Chang, Taipei (TW); Jih-Wen Chou, Hsinchu (TW); Hwi-Huang Chen, Hsinchu (TW); Hsin-Hong Chen, Hsinchu (TW); and Yu-Jen Huang, Hsinchu (TW)
Assigned to Powerchip Semiconductor Manufacturing Corporation, Hsinchu (TW)
Filed by Powerchip Semiconductor Manufacturing Corporation, Hsinchu (TW)
Filed on Dec. 14, 2022, as Appl. No. 18/080,745.
Claims priority of application No. 111139046 (TW), filed on Oct. 14, 2022.
Prior Publication US 2024/0128341 A1, Apr. 18, 2024
Int. Cl. H01L 29/423 (2006.01); H10D 30/01 (2025.01); H10D 30/47 (2025.01); H10D 64/01 (2025.01); H10D 64/27 (2025.01)
CPC H10D 64/411 (2025.01) [H10D 30/015 (2025.01); H10D 30/475 (2025.01); H10D 64/01 (2025.01)] 10 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a base pattern comprising a channel region and a drain region adjacent to the channel region;
a first semiconductor layer disposed on the channel region of the base pattern; and
a gate structure disposed on the first semiconductor layer and comprising:
a first stack disposed on the first semiconductor layer and comprising a second semiconductor layer and a third semiconductor layer on the second semiconductor layer; and
a second stack disposed on the first stack and comprising a fourth semiconductor layer on the third semiconductor layer and a conductive layer on the fourth semiconductor layer,
wherein the first stack comprises a first sidewall adjacent to the drain region and a second sidewall opposite to the first sidewall in a first direction parallel to a top surface of the base pattern, the first sidewall is in a first distance from the second stack in the first direction, the second sidewall is in a second distance from the second stack in the first direction, the first distance and the second distance are positive numbers being greater than 0, and the first distance is greater than the second distance,
wherein each of the first semiconductor layer and the third semiconductor layer comprises a first element doped therein, and a concentration of the first element doped in the first semiconductor layer is greater than a concentration of the first element doped in the third semiconductor layer, and
wherein each of the second semiconductor layer and the fourth semiconductor layer comprises a second element doped therein, a concentration of the second element doped in the second semiconductor layer is less than a concentration of the second element doped in the fourth semiconductor layer.