US 12,471,349 B2
Contact over active gate structures with uniform and conformal gate insulating cap layers for advanced integrated circuit structure fabrication
Leonard P. Guler, Hillsboro, OR (US); Chanaka D. Munasinghe, Portland, OR (US); Charles H. Wallace, Portland, OR (US); Tahir Ghani, Portland, OR (US); and Krishna Ganesan, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 11, 2022, as Appl. No. 17/693,124.
Prior Publication US 2023/0290843 A1, Sep. 14, 2023
Int. Cl. H10D 64/23 (2025.01); H10D 30/62 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01)
CPC H10D 64/259 (2025.01) [H10D 30/6735 (2025.01); H10D 62/121 (2025.01); H10D 30/6219 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a gate structure;
an epitaxial source or drain structure laterally spaced apart from the gate structure;
a dielectric spacer laterally between the gate structure and the epitaxial source or drain structure, the dielectric spacer having an uppermost surface below an uppermost surface of the gate structure; and
a gate insulating cap layer on the uppermost surface of the gate structure and along upper portions of sides of the gate structure, the gate insulating cap layer along an upper portion of a side of the dielectric spacer, and the gate insulating cap layer distinct from the dielectric spacer.