US 12,471,347 B2
Vertical power semiconductor device and manufacturing method thereof
Jie Li, New Taipei (TW); Ming-Wei Tsai, New Taipei (TW); Chiao-Shun Chuang, New Taipei (TW); and Ching-Wen Wang, New Taipei (TW)
Assigned to Diodes Incorporated, Plano, TX (US)
Filed by Diodes Incorporated, Plano, TX (US)
Filed on Dec. 4, 2024, as Appl. No. 18/969,220.
Claims priority of application No. 202311713529.3 (CN), filed on Dec. 13, 2023.
Prior Publication US 2025/0203998 A1, Jun. 19, 2025
Int. Cl. H10D 64/23 (2025.01); H10D 30/01 (2025.01); H10D 30/66 (2025.01); H10D 62/00 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 62/832 (2025.01); H10D 64/01 (2025.01)
CPC H10D 64/252 (2025.01) [H10D 30/0291 (2025.01); H10D 30/66 (2025.01); H10D 62/01 (2025.01); H10D 62/127 (2025.01); H10D 62/153 (2025.01); H10D 62/154 (2025.01); H10D 62/8325 (2025.01); H10D 64/01 (2025.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate comprising a first surface and a second surface opposite the first surface;
a first gate structure and a second gate structure located over the first surface of the substrate;
a first dielectric layer covering the first gate structure, the second gate structure, and portions of the first surface of the substrate;
a current spreading layer located between the first gate structure and the second gate structure, wherein at least a portion of the current spreading layer is located in the substrate;
a conductive plug located on the current spreading layer, wherein the current spreading layer has a first width larger than a second width of a bottom of the conductive plug; and
a second dielectric layer covering the first dielectric layer and surrounding the conductive plug, wherein a portion of the second dielectric layer separates the conductive plug from the first dielectric layer.