| CPC H10D 64/033 (2025.01) [G11C 11/223 (2013.01); G11C 11/2255 (2013.01); G11C 11/2257 (2013.01); H10D 30/6755 (2025.01); H10D 30/701 (2025.01); H10D 64/689 (2025.01)] | 20 Claims |
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1. A method, comprising:
patterning a first trench extending through a first conductive line;
depositing a memory film along sidewalls and a bottom surface of the first trench;
depositing an oxide semiconductor (OS) layer over the memory film, the OS layer extending along the sidewalls and the bottom surface of the first trench;
depositing a first dielectric material over and contacting the OS layer, wherein depositing the first dielectric material comprises simultaneously supplying a first hydrogen-comprising precursor at a first flow rate and a second hydrogen-free precursor at a second flow rate, wherein a ratio of the second flow rate of the second hydrogen-free precursor to the first flow rate of the first hydrogen-comprising precursor is at least 60, and wherein after depositing the first dielectric material, a hydrogen concentration at an interface between the first dielectric material and the OS layer is 3 at % or less;
depositing a second dielectric material over the first dielectric material to fill a remaining portion of the first trench;
etching a second trench through the first dielectric material and the second dielectric material, wherein the first trench extends through the OS layer; and
filling the second trench with a first conductive material to form a bit line, wherein the bit line extends through the OS layer and overlaps the OS layer.
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