| CPC H10D 64/017 (2025.01) [H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01)] | 20 Claims |
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1. A manufacturing method of a semiconductor device, the method comprising:
alternately stacking a plurality of subgate sacrificial patterns and a plurality of semiconductor patterns on a substrate;
forming a plurality of main gate sacrificial patterns spaced apart from each other on a stacked structure of the subgate sacrificial patterns and the semiconductor patterns;
forming a first insulating layer between the main gate sacrificial patterns;
removing the main gate sacrificial patterns;
removing the subgate sacrificial patterns;
forming a main gate dummy pattern in a space from which the main gate sacrificial patterns are removed;
forming a plurality of subgate dummy patterns in a space from which the subgate sacrificial patterns are removed;
removing the first insulating layer;
forming a recess under a space where the first insulating layer is removed;
forming a source/drain pattern within the recess;
forming a second insulating layer on the source/drain pattern;
removing the main gate dummy pattern and the subgate dummy patterns; and
forming a gate electrode in a space where the main gate dummy pattern and the subgate dummy patterns are removed.
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