US 12,471,343 B2
Gate isolation features in semiconductor devices and methods of fabricating the same
Shao-Jyun Wu, New Taipei (TW); Yung Feng Chang, Hsinchu (TW); Tung-Heng Hsieh, Hsinchu County (TW); and Bao-Ru Young, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Feb. 25, 2022, as Appl. No. 17/680,615.
Claims priority of provisional application 63/211,714, filed on Jun. 17, 2021.
Claims priority of provisional application 63/211,756, filed on Jun. 17, 2021.
Prior Publication US 2022/0406900 A1, Dec. 22, 2022
Int. Cl. H10D 64/01 (2025.01); H01L 21/762 (2006.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01)
CPC H10D 64/01 (2025.01) [H01L 21/762 (2013.01); H10D 30/6735 (2025.01); H10D 62/118 (2025.01); H10D 64/017 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a first semiconductor fin and a second semiconductor fin protruding from a substrate, wherein each of the first and the second semiconductor fins includes a stack of alternating channel layers and non-channel layers;
forming a dielectric helmet between and protruding from the first and the second semiconductor fins;
forming a dummy gate stack over the dielectric helmet;
patterning the dummy gate stack to expose a portion of the dielectric helmet;
removing the exposed portion of the dielectric helmet;
forming a metal gate structure in place of the dummy gate stack and the non-channel layers, such that a remaining portion of the dielectric helmet separates the metal gate structure between the first and the second semiconductor fins; and
forming a contact feature over a portion of the metal gate structure, wherein a sidewall of the contact feature is between one of the first or the second semiconductor fin and the remaining portion of the dielectric helmet.