| CPC H10D 62/8503 (2025.01) [H01L 21/0254 (2013.01); H10D 30/015 (2025.01); H10D 30/47 (2025.01); H10D 30/60 (2025.01); H10D 30/475 (2025.01)] | 19 Claims |

|
1. A method of fabricating a semiconductor device, the method comprising:
epitaxially growing a multilayer Group III nitride structure on a first surface of a substrate, the first surface being capable of supporting the epitaxial growth of at least one Group III nitride layer;
removing portions of the multilayer Group III nitride structure to form at least one mesa arranged on the first surface, the mesa comprising the epitaxial Group III nitride-based multi-layer structure and being laterally spaced part by a portion of the substrate;
applying insulating material to the first surface of the substrate so that side faces of the mesa are embedded in the insulating material;
forming a first electrode on a top surface of the mesa;
forming a first via in the insulating material that extends from a top surface of the insulating material to the first surface of the substrate;
inserting conductive material into the first via to form a first conductive via;
applying an electrically conductive redistribution structure to an upper surface comprising the top surface of the mesa and the top surface of the insulating material, and electrically connecting the first conductive via to the first electrode; and
successively removing portions of a second surface of the substrate, the second surface opposing the first surface, to expose the insulating material and form a worked second surface comprising the insulating material.
|