| CPC H10D 62/8325 (2025.01) [H10D 8/60 (2025.01); H10D 62/106 (2025.01); H10D 64/519 (2025.01); H10D 64/62 (2025.01); H10D 84/146 (2025.01)] | 12 Claims |
|
1. A semiconductor device comprising:
a plurality of transistor regions;
at least one diode region; and
a peripheral region surrounding the transistor regions and the at least one diode region,
wherein the transistor regions include:
a silicon carbide layer having a first plane and a second plane facing the first plane, the silicon carbide layer including a first silicon carbide region of n-type having a plurality of first portions in contact with the first plane, a second silicon carbide region of p-type provided between the first silicon carbide region and the first plane, the second silicon carbide region including a first low-concentration portion and a first high-concentration portion provided between the first low-concentration portion and the first plane, the first high-concentration portion having p-type impurity concentration higher than p-type impurity concentration of the first low-concentration portion, and a third silicon carbide region of n-type provided between the second silicon carbide region and the first plane;
a first electrode in contact with the first portions, the second silicon carbide region, and the third silicon carbide region;
a second electrode in contact with the second plane;
a gate electrode facing the second silicon carbide region; and
a gate insulating layer provided between the gate electrode and the second silicon carbide region,
wherein the at least one diode region includes:
the silicon carbide layer including the first silicon carbide region of n-type having a plurality of second portions in contact with the first plane and a fourth silicon carbide region of p-type provided between the first silicon carbide region and the first plane, the fourth silicon carbide region having a second low-concentration portion and a second high-concentration portion provided between the second low-concentration portion and the first plane, the second high-concentration portion having p-type impurity concentration higher than p-type impurity concentration of the second low-concentration portion;
the first electrode in contact with the second portions and the fourth silicon carbide region; and
the second electrode,
wherein the peripheral region includes:
the silicon carbide layer;
a gate electrode pad provided on a side of the first plane with respect to the silicon carbide layer; and
a gate wiring configured to electrically connect the gate electrode pad to the gate electrode and formed to extend in a first direction parallel to the first plane,
wherein an occupied area per unit area of the fourth silicon carbide region projected onto the first plane is larger than an occupied area per the unit area of the second silicon carbide region projected onto the first plane,
wherein a first diode region being one of the at least one diode region is provided between a first transistor region and a second transistor region, the first transistor region is one of the transistor regions, the second transistor region is one of the transistor regions provided in the first direction with respect to the first transistor region, and
wherein a distance in a second direction parallel to the first plane and perpendicular to the first direction between the second high-concentration portion in the first diode region and the gate wiring is larger than a distance in the second direction between the first high-concentration portion in the first transistor region and the gate wiring.
|