| CPC H10D 62/121 (2025.01) [H10D 62/102 (2025.01)] | 20 Claims |

|
1. A field effect transistor, comprising: a substrate structure, a source, a drain, and a gate, wherein:
the source and the drain are arranged on the substrate structure in a first direction, and a channel region is formed between the source and the drain;
a channel layer is formed in the channel region, N carbon nanotubes extending in the first direction are embedded in the channel layer, wherein N is an integer greater than or equal to 1, and two ends of each of the N carbon nanotubes are respectively connected to the source and the drain to form a conductive path, and wherein a first contact layer is disposed on a side that is of the source and that faces the channel layer, and a second contact layer is disposed on a side that is of the drain and that faces the channel layer; and
the gate is formed on the channel layer.
|