US 12,471,330 B2
Integrated circuit structures having maximized channel sizing
Sukru Yemenicioglu, Portland, OR (US); Tahir Ghani, Portland, OR (US); Andy Chih-Hung Wei, Yamhill, OR (US); Leonard P. Guler, Hillsboro, OR (US); Charles H. Wallace, Portland, OR (US); and Mohit K. Haran, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 10, 2021, as Appl. No. 17/547,992.
Prior Publication US 2023/0187494 A1, Jun. 15, 2023
Int. Cl. H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01)
CPC H10D 62/121 (2025.01) [H10D 30/6713 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a first vertical stack of horizontal nanowires having a first width;
a second vertical stack of horizontal nanowires spaced apart from and parallel with the first vertical stack of horizontal nanowires and having the first width;
a first gate structure, comprising:
a first gate structure portion over the first vertical stack of horizontal nanowires;
a second gate structure portion over the second vertical stack of horizontal nanowires; and
a gate cut between the first gate structure portion and the second gate structure portion;
a third vertical stack of horizontal nanowires having a second width greater than the first width, the third vertical stack of horizontal nanowires having a longest dimension along a same axis as a longest dimension of the first vertical stack of horizontal nanowires;
a fourth vertical stack of horizontal nanowires spaced apart from and parallel with the third vertical stack of horizontal nanowires and having the second width, the fourth vertical stack of horizontal nanowires having a longest dimension along a same axis as a longest dimension of the second vertical stack of horizontal nanowires; and
a second gate structure continuous over the third vertical stack of horizontal nanowires and over the fourth vertical stack of horizontal nanowires.