US 12,471,329 B2
Semiconductor structures and manufacturing method thereof
Shih-Jung Tu, Tainan (TW); Po-Wei Liu, Tainan (TW); Tsung-Yu Yang, Tainan (TW); Yun-Chi Wu, Tainan (TW); and Chien Hung Liu, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Jan. 11, 2023, as Appl. No. 18/153,335.
Claims priority of provisional application 63/375,873, filed on Sep. 16, 2022.
Prior Publication US 2024/0096941 A1, Mar. 21, 2024
Int. Cl. H01L 21/76 (2006.01); H01L 21/762 (2006.01); H01L 23/52 (2006.01); H01L 23/522 (2006.01); H10D 62/10 (2025.01)
CPC H10D 62/115 (2025.01) [H01L 21/76224 (2013.01); H01L 23/5226 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate comprising a first surface and a second surface opposite to the first surface;
a first and a second shallow trench isolations disposed in the substrate and on the second surface;
a deep trench isolation structure in the substrate and coupled to the first shallow trench isolation;
a first dielectric layer disposed on the first surface and coupled to the deep trench isolation structure;
a second dielectric layer disposed over the first dielectric layer and coupled to the deep trench isolation structure;
a third dielectric layer comprising a horizontal portion disposed over the second dielectric layer and a vertical portion coupled to the horizontal portion; and
a through substrate via structure penetrating the substrate from the first surface to the second surface and penetrating the second shallow trench isolation, wherein the vertical portion of the third dielectric layer surrounds the through substrate via structure.