| CPC H10D 62/106 (2025.01) [H01L 21/02554 (2013.01); H10D 62/125 (2025.01)] | 16 Claims |
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1. A power semiconductor device comprising:
a semiconductor substrate comprising a first region of a first conductivity type, the semiconductor substrate comprising an active region and an edge termination region surrounding the active region, wherein the edge termination region is located laterally between the active region and a side surface of the power semiconductor device;
a first region of a second conductivity type located in the active region and above the first region of the first conductivity type;
an edge termination structure comprising one or more regions of the second conductivity type located in the edge termination region of the semiconductor substrate and extending to an upper surface of the semiconductor substrate;
a plurality of oxide segments located over the upper surface of the edge termination region of the semiconductor substrate, wherein the plurality of oxide segments are laterally spaced from each other; and
a charge dissipation layer located over the upper surface of the edge termination region of the semiconductor substrate and the plurality of oxide segments, such that the charge dissipation layer is in contact with the upper surface of the semiconductor substrate only at a plurality of interface regions, wherein the interface regions comprise regions of the semiconductor substrate located laterally between adjacent oxide segments,
wherein the edge termination structure further comprises:
a plurality of second regions of the second conductivity type, wherein the second regions of the second conductivity type are laterally spaced from each other; and
a plurality of third regions of the second conductivity type having a higher doping concentration than the plurality of second regions of the second conductivity type, wherein each third region of the second conductivity type is in contact with a corresponding second region of the second conductivity type;
wherein the second regions of the second conductivity type are located such that each second region of the second conductivity type is located at least partially below only one oxide segment and a portion of the charge dissipation layer between adjacent oxide segments, such that each oxide segment is located laterally between the side surface of the semiconductor device and a corresponding second region of the second conductivity type, and
wherein each third region of the second conductivity type is located at an interface region.
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