US 12,471,323 B2
Semiconductor device and method of fabricating the same
Dongsuk Shin, Suwon-si (KR); Hyun-Kwan Yu, Suwon-si (KR); Sunyoung Lee, Yongin-si (KR); Ji Hoon Cha, Seoul (KR); and Kyungyeon Hwang, Yongin-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Aug. 17, 2022, as Appl. No. 17/889,744.
Claims priority of application No. 10-2022-0007410 (KR), filed on Jan. 18, 2022; and application No. 10-2022-0039763 (KR), filed on Mar. 30, 2022.
Prior Publication US 2023/0231049 A1, Jul. 20, 2023
Int. Cl. H10D 30/69 (2025.01); H10D 62/10 (2025.01); H10D 64/27 (2025.01); H10D 64/68 (2025.01)
CPC H10D 30/721 (2025.01) [H10D 62/115 (2025.01); H10D 64/514 (2025.01); H10D 64/683 (2025.01)] 13 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a substrate that includes an active pattern;
a channel pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns that are vertically stacked and spaced apart from each other;
a source/drain pattern connected to the plurality of semiconductor patterns;
a gate electrode on the plurality of semiconductor patterns; and
a gate dielectric layer between the gate electrode and the plurality of semiconductor patterns,
wherein the gate electrode includes a first portion between a first semiconductor pattern and a second semiconductor pattern that are adjacent ones of the plurality of semiconductor patterns, the first portion having a sidewall that is convex, and a second portion on an uppermost semiconductor pattern of the plurality of semiconductor patterns,
wherein the gate dielectric layer includes:
a high-k dielectric layer that surrounds the first portion of the gate electrode; and
an inner spacer on the high-k dielectric layer,
wherein the inner spacer includes:
a horizontal portion between the high-k dielectric layer and the second semiconductor pattern, the horizontal portion having a first thickness;
a vertical portion between the high-k dielectric layer and the source/drain pattern, the vertical portion having a second thickness; and
a corner portion between the horizontal portion and the vertical portion, the corner portion having a third thickness,
wherein the first thickness is less than the second thickness,
wherein the second thickness is less than the third thickness,
wherein the inner spacer between the second portion and the uppermost semiconductor pattern has a fourth thickness,
wherein the inner spacer between the second portion and a gate spacer has a fifth thickness,
wherein the inner spacer between the second portion and an inside corner where the uppermost semiconductor pattern contacts the gate spacer has a sixth thickness,
wherein the fourth thickness is less than the fifth thickness, and
wherein the fifth thickness is less than the sixth thickness.