US 12,471,322 B2
Horizontal GAA nano-wire and nano-slab transistors
Benjamin Colombeau, San Jose, CA (US); and Hans-Joachim Gossmann, Summit, NJ (US)
Assigned to Applied Materials, Inc., Santa Clara, CA (US)
Filed by Applied Materials, Inc., Santa Clara, CA (US)
Filed on Sep. 29, 2022, as Appl. No. 17/956,061.
Application 17/956,061 is a continuation of application No. 17/073,505, filed on Oct. 19, 2020, granted, now 11,495,500.
Claims priority of provisional application 63/014,389, filed on Apr. 23, 2020.
Claims priority of provisional application 62/924,120, filed on Oct. 21, 2019.
Prior Publication US 2023/0014586 A1, Jan. 19, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 30/67 (2025.01); H01L 21/02 (2006.01); H01L 21/324 (2006.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 30/6757 (2025.01) [H01L 21/0245 (2013.01); H01L 21/02532 (2013.01); H01L 21/324 (2013.01); H10D 30/6735 (2025.01); H10D 62/119 (2025.01); H10D 84/0128 (2025.01); H10D 84/038 (2025.01)] 20 Claims
OG exemplary drawing
 
13. A horizontal gate-all-around device comprising:
a superlattice structure between a source region and a drain region on a substrate, the superlattice structure comprising a plurality of horizontal doped semiconductor material layers, an oxide layer on the plurality of horizontal doped semiconductor material layers, a high-k dielectric layer on the oxide layer, and conductive layer on the high-k dielectric layer, the plurality of horizontal doped semiconductor material layers having a homogeneous concentration of dopant; and
a gate electrode on the substrate and surrounding each of the plurality of horizontal doped semiconductor material layers.