US 12,471,318 B2
Low defect, high mobility thin film transistors with in-situ doped metal oxide channel material
Chieh-Jen Ku, Hillsboro, OR (US); Andre Baran, Portland, OR (US); Bernhard Sell, Portland, OR (US); David Goldstein, Beaverton, OR (US); and Timothy Jen, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on May 5, 2021, as Appl. No. 17/308,856.
Prior Publication US 2022/0359759 A1, Nov. 10, 2022
Int. Cl. H10D 30/67 (2025.01); H01L 21/02 (2006.01); H10D 64/68 (2025.01); H10D 87/00 (2025.01); H10D 99/00 (2025.01)
CPC H10D 30/6755 (2025.01) [H01L 21/02565 (2013.01); H01L 21/02614 (2013.01); H10D 30/6757 (2025.01); H10D 64/691 (2025.01); H10D 87/00 (2025.01); H10D 99/00 (2025.01)] 13 Claims
OG exemplary drawing
 
1. A transistor structure, comprising:
a first source or drain contact;
a gate electrode material layer over the first source or drain contact;
a gate insulator lining a via through a thickness of the gate electrode material layer and in contact with a sidewall of the gate electrode material layer;
a channel material comprising a first portion lining a sidewall of the gate insulator within the via and a second portion over, and in contact with, the first source or drain contact at a bottom of the via, the first and second portions of the channel material comprising O, In, Ga, Zn, and Al with an atomic composition ratio of Ga to each of In and Zn of 1.5-2.5, and an atomic composition ratio of Ga to Al of 8-50, the first portion of the channel material of a first layer thickness, and the second portion of the channel material of a second layer thickness, wherein the first layer thickness is within 5% of the second layer thickness; and
a second source contact or drain contact electrically coupled to the channel material.