US 12,471,317 B2
Semiconductor device having fin structure including dielectric-containing substrate with semiconductor surface and method of forming the same
Ka-Hing Fung, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Nov. 28, 2023, as Appl. No. 18/521,381.
Application 18/521,381 is a continuation of application No. 17/699,920, filed on Mar. 21, 2022, granted, now 11,854,900.
Application 17/699,920 is a continuation of application No. 16/926,165, filed on Jul. 10, 2020, granted, now 11,282,748, issued on Mar. 22, 2022.
Claims priority of provisional application 62/906,287, filed on Sep. 26, 2019.
Prior Publication US 2024/0105519 A1, Mar. 28, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 30/67 (2025.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H10D 30/01 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 30/6735 (2025.01) [H01L 21/02532 (2013.01); H01L 21/02603 (2013.01); H01L 21/30604 (2013.01); H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6757 (2025.01); H10D 30/6758 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01)] 20 Claims
OG exemplary drawing
 
12. A semiconductor device, comprising:
a dielectric layer disposed over a semiconductor substrate;
a semiconductor-containing substrate disposed on the dielectric layer;
channel layers vertically suspended over the semiconductor-containing substrate, a bottom-most channel layer being vertically separated from the semiconductor-containing substrate by a space;
a first source/drain (S/D) feature disposed over the semiconductor substrate and contacting first ends of the channel layers;
a second S/D feature disposed over the semiconductor substrate and contacting second ends of the channel layers;
a gate dielectric layer disposed on and wrapping each of the channel layers; and
a gate electrode layer disposed on the gate dielectric layer and wrapping each of the channel layers, wherein a portion of the gate dielectric layer and the gate electrode layer wrapping the bottom-most channel layer is located in the space between the semiconductor-containing substrate and the bottom-most channel layer, and wherein the first and second S/D features physically contact the semiconductor substrate.