| CPC H10D 30/6735 (2025.01) [H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6739 (2025.01); H10D 64/015 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01); H10D 64/021 (2025.01); H10D 84/0135 (2025.01); H10D 84/0144 (2025.01); H10D 84/0149 (2025.01); H10D 84/038 (2025.01); H10D 62/121 (2025.01); H10D 84/0128 (2025.01)] | 20 Claims |
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9. A method of manufacturing a semiconductor device, comprising:
forming gate structures over a substrate, each of which includes a plurality of semiconductor sheets vertically arranged over a bottom fin structure, a gate dielectric layer wrapping around each of the plurality of semiconductor sheets, and a gate electrode disposed over the gate dielectric layer;
forming a source/drain structure;
forming a gate cap conductive layer over the gate electrode;
forming a hard mask layer over the gate structures after the gate cap conductive layer is formed;
replacing the bottom fin structure with a dielectric fin structure;
forming spacers on opposite sides of the dielectric fin structure;
forming a first trench by etching the gate electrode using the dielectric fin structure and the spacers as an etching mask until the gate cap conductive layer is exposed;
filling the first trench with a first dielectric material;
patterning the hard mask layer, thereby forming a first opening and a second opening;
removing an underlying structure through the first opening and the second opening, thereby forming a second trench and a third trench; and
filling the second trench and the third trench with a second dielectric material.
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