| CPC H10D 30/6735 (2025.01) [H10B 12/05 (2023.02); H10B 12/315 (2023.02); H10B 12/482 (2023.02); H10B 12/488 (2023.02); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 64/666 (2025.01); H10D 64/667 (2025.01)] | 7 Claims |
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1. A method for fabricating a semiconductor structure, comprising:
providing a substrate;
forming a plurality of active pillars arranged in an array in the substrate, each of the plurality of active pillars extending along a direction perpendicular to the substrate; wherein the forming a plurality of active pillars arranged in an array in the substrate comprises:
forming a plurality of first grooves spaced along a first direction in the substrate, the plurality of first grooves extending along a second direction, an area between adjacent two of the plurality of first grooves constituting an active strip, and the first direction intersecting with the second direction;
forming a spacer in each of the plurality of first grooves, a top surface of the spacer being flush with a top surface of the substrate; wherein the spacer comprises a first spacer and the second spacer sequentially arranged in a stack, and the first spacer is arranged on the substrate;
forming a plurality of second grooves spaced along the second direction in the substrate, each of the plurality of second grooves extending along the first direction, a depth of a given one of the plurality of second groove being smaller than a depth of a given one of the plurality of first groove, reserved part of the active strips constituting a plurality of initial active pillars arranged in an array, and reserved part of second spacers constituting a plurality of isolation pillars spaced; and
performing ion implantation on the plurality of initial active pillars to form the plurality of active pillars;
forming a protective layer respectively on a top surface of a given one of the plurality of initial active pillars and on a top surface of a given one of the plurality of isolation pillars;
forming a plurality of bit lines spaced along the first direction in the substrate, each of the plurality of bit lines extending along the second direction;
removing the protective layers and the plurality of isolation pillars, the first spacer and the plurality of active pillars enclosing to form a filling region; and
forming a gate arranged around each of the plurality of active pillars, a projection of the gate on a given one of the plurality of active pillars covering a channel region of the given active pillar, wherein along the direction perpendicular to the substrate, the gate comprises a first conductive layer and a second conductive layer sequentially arranged in a stack, and a work function of the first conductive layer being different from a work function of the second conductive layer; wherein the forming a gate arranged around each of the plurality of active pillars comprises:
forming a gate oxide layer on a sidewall of the given active pillar;
sequentially forming a first initial insulating layer, a first initial conductive layer, a second initial conductive layer and a second initial insulating layer in the filling region, a top surface of the second initial insulating layer being flush with the top surface of the substrate;
forming a third groove extending along the first direction in the second initial insulating layer, the third groove exposing the second initial conductive layer between adjacent two of the plurality of active pillars in the second direction; and
removing the second initial conductive layer exposed in the third groove, the first initial conductive layer and part of the first initial insulating layer, a reserved part of the first initial conductive layer and a reserved part of the second initial conductive layer being used as the first conductive layer and the second conductive layer respectively, and the first conductive layer and the second conductive layer constituting word lines, each of the word lines comprising a gate around each of the plurality of active pillars and a conductive segment configured to connect each of the gates along the first direction.
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