US 12,471,306 B2
Semiconductor device active region profile and method of forming the same
Feng-Ching Chu, Hsinchu (TW); Wei-Yang Lee, Hsinchu (TW); and Chia-Pin Lin, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jun. 17, 2024, as Appl. No. 18/745,323.
Application 18/745,323 is a continuation of application No. 18/066,188, filed on Dec. 14, 2022, granted, now 12,027,626.
Application 18/066,188 is a continuation of application No. 17/318,362, filed on May 12, 2021, granted, now 11,575,047, issued on Feb. 7, 2023.
Prior Publication US 2024/0339541 A1, Oct. 10, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 30/00 (2025.01); H01L 21/3065 (2006.01); H01L 21/3213 (2006.01); H01L 21/762 (2006.01); H10D 30/01 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01)
CPC H10D 30/506 (2025.01) [H01L 21/3065 (2013.01); H01L 21/32134 (2013.01); H01L 21/76224 (2013.01); H10D 30/0194 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
providing a semiconductor stack over a substrate, the semiconductor stack having first and second semiconductor layers stacked in an interleaving fashion, the first and second semiconductor layers having different materials;
etching the semiconductor stack as part of a first etching process;
etching the semiconductor stack as part of a second etching process, wherein the second etching process has a lateral etch rate greater than that of the first etching process; and
repeating the first etching process and the second etching process to form a trench that extends into the substrate; and
forming a cladding layer in the trench, wherein a sidewall of the cladding layer and a horizontal portion of the cladding layer form an angle less than 90 degrees.