US 12,471,305 B2
Water and ion barrier for III-V semiconductor devices
Gerhard Prechtl, Rosegg (AT); and Oliver Haeberlen, St. Magdalen (AT)
Assigned to Infineon Technologies Austria AG, Villach (AT)
Filed by Infineon Technologies Austria AG, Villach (AT)
Filed on Jan. 24, 2023, as Appl. No. 18/100,620.
Application 18/100,620 is a division of application No. 14/869,457, filed on Sep. 29, 2015, abandoned.
Prior Publication US 2023/0163209 A1, May 25, 2023
Int. Cl. H10D 30/47 (2025.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H10D 30/01 (2025.01); H10D 62/824 (2025.01); H10D 62/85 (2025.01); H10D 64/00 (2025.01)
CPC H10D 30/4755 (2025.01) [H01L 23/564 (2013.01); H10D 30/015 (2025.01); H10D 30/475 (2025.01); H10D 62/824 (2025.01); H01L 23/3192 (2013.01); H10D 62/8503 (2025.01); H10D 64/111 (2025.01)] 22 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
an III-V semiconductor body;
a device having a source, a drain and a two-dimensional charge carrier gas channel formed in the III-V semiconductor body;
one or more metal layers above the III-V semiconductor body;
an interlayer dielectric adjacent each metal layer;
a plurality of vias electrically connecting at least one of the one or more metal layers to the source and the drain of the device formed in the III-V semiconductor body;
a passivation layer touching and being supported by a top surface of the III-V semiconductor body, wherein the lowermost interlayer dielectric is touching and being supported by a top surface of the passivation layer, wherein the passivation layer is an ineffective barrier against diffusion of water, water ions, sodium ions and potassium ions into the III-V semiconductor body; and
a barrier interposed between a first oxide layer and a second oxide layer of the lowermost interlayer dielectric, the barrier configured to prevent water, water ions, sodium ions and potassium ions from diffusing into the first oxide layer of the lowermost interlayer dielectric which is immediately below the barrier.