| CPC H10D 30/475 (2025.01) [H10D 30/015 (2025.01); H10D 64/01 (2025.01); H10D 64/411 (2025.01)] | 10 Claims |

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1. A high electron mobility transistor (HEMT) device, comprising:
a substrate having at least one active region;
a channel layer disposed on the at least one active region;
a barrier layer disposed on the channel layer; and
a gate structure disposed on the barrier layer and extended along a first direction in a top view, wherein the gate structure comprises:
a metal layer; and
a P-type group III-V semiconductor layer vertically disposed between the metal layer and the barrier layer, wherein the P-type group III-V semiconductor layer comprises a lower portion and an upper portion on the lower portion, and the upper portion has a top area greater than a top area of the lower portion, wherein
an area of the metal layer is greater than a top area of the P-type group III-V semiconductor layer.
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