US 12,471,296 B2
High bandwidth memory stack with side edge interconnection and 3D IC structure with the same
Ho-Ming Tong, Taipei (TW); and Chao-Chun Lu, Hsinchu (TW)
Assigned to ND-HI TECHNOLOGIES LAB, INC., Taipei (TW); and ETRON TECHNOLOGY, INC., Hsinchu (TW)
Filed by ND-HI TECHNOLOGIES LAB, INC., Taipei (TW); and ETRON TECHNOLOGY, INC., Hsinchu (TW)
Filed on Feb. 25, 2025, as Appl. No. 19/062,566.
Application 19/062,566 is a continuation in part of application No. 18/471,670, filed on Sep. 21, 2023.
Claims priority of provisional application 63/733,458, filed on Dec. 13, 2024.
Claims priority of provisional application 63/409,852, filed on Sep. 26, 2022.
Prior Publication US 2025/0194114 A1, Jun. 12, 2025
Int. Cl. H10B 80/00 (2023.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01)
CPC H10B 80/00 (2023.02) [H01L 25/0652 (2013.01); H01L 25/18 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06551 (2013.01); H01L 2225/06589 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An IC structure comprising:
a memory stack comprising:
a plurality of semiconductor dies horizontally separate with each other, wherein each semiconductor die comprises a top surface, a bottom surface opposite to the top surface, and four sidewalls with a first sidewall, a second sidewall, a third sidewall and a fourth sidewall, and a plurality of edge pads arranged on the first sidewall of each semiconductor die; wherein the area of the bottom surface or the top surface of each semiconductor die is larger than that of any sidewall; and
a logic die with memory controller and processor circuit under the memory stack and electrically connected to the plurality of edge pads of each semiconductor die; and
a packaging substrate under and electrically connected to the logic die with memory controller and processor;
wherein there is no interposer between the packaging substrate and the logic die with memory controller and processor circuit, and there is no TSV in each semiconductor die.