US 12,471,295 B2
Microelectronic devices with tier stacks with varied tier thicknesses, and related methods and systems
John D. Hopkins, Meridian, ID (US); and Nancy M. Lomeli, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jul. 25, 2022, as Appl. No. 17/814,765.
Application 17/814,765 is a division of application No. 16/904,353, filed on Jun. 17, 2020, granted, now 11,398,486.
Prior Publication US 2022/0359539 A1, Nov. 10, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 69/00 (2023.01); H10B 41/20 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/20 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01)
CPC H10B 69/00 (2023.02) [H10B 41/20 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/20 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A microelectronic device, comprising:
a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers, the stack structure having a lower portion and an upper portion, at least some of the conductive structures providing word lines,
the lower portion comprising some of the insulative structures and some of the conductive structures providing some of the word lines,
the upper portion comprising some other of the insulative structures and some other of the conductive structures providing some other of the word lines,
the some of the insulative structures vertically spacing the some of the word lines from one another within the lower portion of the stack structure being thicker than the some other of the insulative structures vertically spacing the some other of the word lines from one another within the upper portion of the stack structure, and
the some of the conductive structures within the lower portion of the stack structure being thicker than the some other of the conductive structures within the upper portion of the stack structure.