US 12,471,293 B2
In-situ low temperature dielectric deposition and selective trim of phase change materials
Luxherta Buzi, Chappaqua, NY (US); Hiroyuki Miyazoe, White Plains, NY (US); Henry K. Utomo, Ridgefield, CT (US); and Matthew Peter Sagianis, Bayside, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Dec. 8, 2021, as Appl. No. 17/544,993.
Prior Publication US 2023/0180487 A1, Jun. 8, 2023
Int. Cl. H10B 63/00 (2023.01); H10B 63/10 (2023.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01); C23C 16/455 (2006.01)
CPC H10B 63/24 (2023.02) [H10B 63/10 (2023.02); H10B 63/30 (2023.02); H10N 70/063 (2023.02); H10N 70/231 (2023.02); H10N 70/826 (2023.02); H10N 70/8828 (2023.02); C23C 16/45536 (2013.01); H10B 63/82 (2023.02)] 9 Claims
OG exemplary drawing
 
1. A method of fabricating a resistive memory semiconductor device comprising:
providing, within a processing chamber, a semiconductor wafer including a trimmed resistive memory device structure having one or more layers of phase change material used to form the resistive memory device, said one or more layers of phase change material having oxidized sidewall surfaces; and
encapsulating said trimmed resistive memory device structure by depositing, within the processing chamber, a layer of dielectric material, and during said encapsulating, simultaneously etching, within the processing chamber, said wafer to selectively remove the oxidized sidewall surfaces of all the one or more layers of said phase change material, wherein said depositing comprises using a plasma enhanced deposition process; and
during said simultaneously etching and depositing: tuning processing parameters for generating a plasma used to selectively etch said oxidized sidewall surfaces of all the one or more layers of said phase change material and for controlling said depositing a layer of dielectric material.