US 12,471,289 B2
Diagonal memory with vertical transistors and wrap-around control lines
Abhishek A. Sharma, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 22, 2021, as Appl. No. 17/558,688.
Prior Publication US 2023/0200084 A1, Jun. 22, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 53/30 (2023.01); H10B 53/10 (2023.01)
CPC H10B 53/30 (2023.02) [H10B 53/10 (2023.02)] 28 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) device, comprising:
a substrate;
a plurality of vertical transistors over the substrate;
a first conductive line having a first longitudinal axis and conductively coupled to gates of a first subset of the plurality of vertical transistors; and
a second conductive line having a second longitudinal axis and wrapping around at least portions of channel materials of a second subset of the plurality of vertical transistors,
wherein at least one of the first longitudinal axis and the second longitudinal axis is not parallel to any edges of the substrate.