US 12,471,288 B2
Three-dimensional nanoribbon-based hysteretic memory
Wilfred Gomes, Portland, OR (US); Uygar E. Avci, Portland, OR (US); and Abhishek A. Sharma, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 7, 2021, as Appl. No. 17/543,809.
Prior Publication US 2023/0180482 A1, Jun. 8, 2023
Int. Cl. H10B 53/20 (2023.01); H10B 53/10 (2023.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01)
CPC H10B 53/20 (2023.02) [H10B 53/10 (2023.02); H10D 30/6713 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) device, comprising:
a plurality of memory cells, wherein an individual memory cell of the plurality of memory cells includes:
a transistor having a channel region, a first region, and a second region, wherein the first region is one of a source region and a drain region of the transistor, and the second region is another one of the source region and the drain region of the transistor, and
a capacitor having a first capacitor electrode, a second capacitor electrode, and a capacitor insulator,
wherein, in the individual memory cell, at least one of the capacitor insulator and a gate stack of the transistor includes a hysteretic material or a hysteretic arrangement, the first capacitor electrode is coupled to the second region, each of the first capacitor electrode and the second capacitor electrode at least partially wraps around a nanoribbon of the individual memory cell, and the first capacitor electrode is closer to the channel region than the second capacitor electrode;
a first conductive line, coupled to the channel regions of a first set of two or more memory cells of the plurality of memory cells;
a second conductive line, coupled to the first regions of a second set of two or more memory cells of the plurality of memory cells; and
a third conductive line, coupled to the second capacitor electrodes of the second set.