| CPC H10B 51/20 (2023.02) [G11C 11/223 (2013.01); G11C 11/2275 (2013.01); H10D 30/701 (2025.01)] | 20 Claims |
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1. A semiconductor device having a nonvolatile memory cell, comprising:
a plurality of first semiconductor layers each extending in a first direction and each configuring a channel region of the nonvolatile memory cell;
a pair of second semiconductor layers provided so as to sandwich the plurality of first semiconductor layers in the first direction, connected to the plurality of first semiconductor layers, and configuring a source region and a drain region of the nonvolatile memory cell;
a plurality of paraelectric films covering outer peripheries of the plurality of first semiconductor layers between the pair of second semiconductor layers, respectively;
a bottom electrode covering outer peripheries of the plurality of paraelectric films between the pair of second semiconductor layers;
a ferroelectric film formed on the bottom electrode; and
a top electrode formed on the ferroelectric film,
wherein a contact area between the bottom electrode and the ferroelectric film is smaller than a contact area between the bottom electrode and the plurality of paraelectric films.
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