| CPC H10B 43/35 (2023.02) [H01L 23/5226 (2013.01); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/40 (2023.02)] | 20 Claims |
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1. A semiconductor device comprising:
a stack on a substrate, the stack including gate electrodes spaced apart from each other in a vertical direction; and
a channel structure penetrating through the stack; and
gate contact plugs contacting the gate electrodes,
wherein the stack includes a lower stack and an upper stack on the lower stack,
wherein the channel structure includes:
a lower channel structure penetrating through the lower stack; and
an upper channel structure penetrating through the upper stack,
wherein the lower channel structure includes:
a lower insulating pattern; and
a lower channel layer on a side surface of the lower insulating pattern,
wherein the upper channel structure includes an upper channel layer electrically connected to the lower channel layer,
wherein the gate electrodes include:
a first gate electrode;
a second gate electrode on the first gate electrode; and
a third gate electrode on the second gate electrode,
wherein the gate contact plugs include:
a first gate contact plug contacting the first gate electrode and having a first width at a first height level;
a second gate contact plug contacting the second gate electrode and having a second maximum width at the first height level; and
a third gate contact plug contacting the third gate electrode and having a third width at the first height level,
wherein the first width is greater than the second width, and
wherein the second width is greater than the third width.
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