US 12,471,283 B2
Microelectronic devices with source region vertical extension between upper and lower channel regions, and related methods
Albert Fayrushin, Boise, ID (US); Haitao Liu, Boise, ID (US); and Chris M. Carlson, Nampa, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 29, 2024, as Appl. No. 18/649,366.
Application 18/649,366 is a continuation of application No. 17/158,859, filed on Jan. 26, 2021, granted, now 11,974,430.
Prior Publication US 2024/0284675 A1, Aug. 22, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 43/27 (2023.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 43/10 (2023.01)
CPC H10B 43/27 (2023.02) [H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 43/10 (2023.02)] 19 Claims
OG exemplary drawing
 
1. A microelectronic device, comprising:
a stack structure comprising vertically repeated tier groups, the tier groups individually comprising at least one conductive structure and at least one insulative structure;
a source region below the stack structure, the source region comprising a doped material; and
at least one pillar extending substantially vertically through the stack structure and through the source region, the at least one pillar individually comprising:
in elevations of the stack structure, an upper region of a channel material horizontally disposed between regions of cell materials and an insulative core region of the at least one pillar, the cell materials extending partially into the doped material of the source region; and
in elevations below the source region, a lower region of the channel material,
the doped material of the source region defining at least one vertical extension between the upper region of the channel material and the lower region of the channel material.