| CPC H10B 43/27 (2023.02) [H10B 41/27 (2023.02)] | 30 Claims |

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1. A method used in forming a memory array comprising strings of memory cells, comprising:
forming a vertical stack comprising alternating first and second tiers directly above a conductor tier, material of the first tiers being of different composition from material of the second tiers, the first tiers and the second tiers comprise memory-block regions having a horizontally-elongated trench laterally-between immediately-laterally-adjacent of the memory-block regions;
the first tiers comprising silicon nitride, at least one of a lower of the first tiers comprising carbon-doped silicon nitride having at least 0.5 atomic percent more carbon than atomic percent of carbon, if any, in the silicon nitride of at least some of the first tiers that are directly above the at least one lower first tier;
through the trenches, replacing one of (a) and (b) with conducting material, where:
(a): the carbon-doped silicon nitride of the at least one lower first tier, or
(b): the silicon nitride of the at least some of the first tiers that are directly above the at least one lower first tier;
through the trenches, replacing the other of the (a) and the (b) with conductive material after the replacing of the one; and
forming channel-material strings through the first tiers and the second tiers, the channel-material of the channel-material strings being directly electrically coupled with conductor material of the conductor tier.
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