US 12,471,279 B2
Channel structures for three-dimensional memory devices and methods for forming the same
Xiaolong Du, Hubei (CN); Wanbo Geng, Hubei (CN); Zhiliang Xia, Hubei (CN); Xiaoxin Liu, Hubei (CN); Tingting Gao, Hubei (CN); and Changzhi Sun, Hubei (CN)
Assigned to Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed by Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed on Mar. 16, 2022, as Appl. No. 17/655,025.
Claims priority of application No. 202110312042.9 (CN), filed on Mar. 24, 2021.
Prior Publication US 2022/0310648 A1, Sep. 29, 2022
Prior Publication US 2023/0276623 A9, Aug. 31, 2023
Int. Cl. H10B 43/27 (2023.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01)
CPC H10B 43/27 (2023.02) [H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method for forming a three-dimensional memory device, comprising:
forming an alternating dielectric stack on a substrate;
forming an opening extending partially through the alternating dielectric stack, wherein the opening exposes sidewalls of the alternating dielectric stack;
disposing a dielectric protection layer in the opening and on the exposed sidewalls of the alternating dielectric stack, the dielectric protection layer having a thickness that decreases along a first direction extending from a top to a bottom of the opening;
forming a plurality of recesses via an etching process on a plurality of first dielectric layers; and
forming channel layers in the plurality of recesses, wherein forming the channel layers comprises:
disposing a blocking layer, a storage layer, and a tunneling layer; and
removing excess material from an outside surface of the plurality of recesses, wherein the storage layer, the blocking layer, and the tunneling layer are formed within the plurality of recesses.