US 12,471,278 B2
Three-dimensional memory device with charge trap layer including carbon region and fabrication method thereof
Qiguang Wang, Wuhan (CN); Hao Pu, Wuhan (CN); Tuo Li, Wuhan (CN); and Yingjie Zhao, Wuhan (CN)
Assigned to Yangtze Memory Technologies Co., Ltd., Wuhan (CN)
Filed by Yangtze Memory Technologies Co., Ltd., Wuhan (CN)
Filed on Dec. 6, 2021, as Appl. No. 17/457,787.
Application 17/457,787 is a continuation of application No. PCT/CN2021/128337, filed on Nov. 3, 2021.
Prior Publication US 2023/0134694 A1, May 4, 2023
Int. Cl. H10B 43/27 (2023.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01)
CPC H10B 43/27 (2023.02) [H10B 43/10 (2023.02); H10B 43/35 (2023.02)] 9 Claims
OG exemplary drawing
 
1. A method for fabricating a three-dimensional (3D) memory device, comprising:
providing a substrate;
forming a layer stack over the substrate;
forming a channel hole, the channel hole extending through the layer stack;
forming a blocking layer on a sidewall of the channel hole;
forming a charge trap layer on the blocking layer, the charge trap layer including a non-carbon region and a carbon region that comprises a certain amount of carbon elements, wherein the non-carbon region of the charge trap layer is in physical contact with the blocking layer, and forming the charge trap layer comprises forming a plurality of layers consecutively on a surface of the blocking layer for forming the non-carbon region, and the plurality of layers includes a silicon nitride layer, a layer of a high-k dielectric material, and a silicon oxynitride layer;
forming a tunnel insulation layer on the charge trap layer, wherein the tunnel insulation layer is in contact with the carbon region of the charge trap layer; and
forming a channel layer on the tunnel insulation layer.