| CPC H10B 41/30 (2023.02) [H10D 30/0411 (2025.01); H10D 30/683 (2025.01); H10D 64/01 (2025.01); H10D 64/251 (2025.01)] | 12 Claims |
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1. A memory device, comprising:
a substrate having a plurality of isolating structures;
a first source/drain region and a plurality of second source/drain regions located in the substrate;
a stack structure located on the substrate between the first source/drain region and the plurality of second source/drain regions;
a first dielectric layer located on the substrate, wherein the first dielectric layer comprises a plurality of dielectric columns separated from each other, and the plurality of dielectric columns are located on the isolating structures;
a first self-aligned contact located on the substrate and connected to the first source/drain region;
a plurality of second self-aligned contacts located between the plurality of dielectric columns on the substrate and connected to the plurality of second source/drain regions;
a first liner structure located between the first self-aligned contact and a first sidewall of the stack structure; and
a second liner structure located between the plurality of second self-aligned contacts and a second sidewall of the stack structure,
wherein the first liner structure and the second liner structure are not connected, and do not cover the stack structure,
wherein the first liner structure and the second liner structure are dielectric materials,
wherein a top surface of the first liner structure and a top surface of the second liner structure are coplanar with a top surface of the plurality of first self-aligned contacts and a top surface of the plurality of second self-aligned contacts.
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