US 12,471,275 B2
Anti-fuse array and memory
Dongbo Zhu, Hefei (CN); Ming-Hui Huang, Hefei (CN); and Tzung-Han Lee, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jan. 8, 2023, as Appl. No. 18/151,452.
Claims priority of application No. 202210923922.4 (CN), filed on Aug. 2, 2022.
Prior Publication US 2024/0049461 A1, Feb. 8, 2024
Int. Cl. H10B 20/25 (2023.01); G11C 17/16 (2006.01); G11C 17/18 (2006.01); H01L 23/525 (2006.01)
CPC H10B 20/25 (2023.02) [G11C 17/16 (2013.01); G11C 17/18 (2013.01); H01L 23/5252 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An anti-fuse array, comprising:
at least a column of first active areas, the first active areas extending along a first direction, each of the first active areas comprising: a first channel region, a first source/drain region and a second source/drain region disposed on two sides of the first channel region, and a first programming region, the first programming region being disposed at an end portion of a given one of the first active areas, and a distance between closest edges of closest end portions of adjacent two of the first active areas being greater than a distance between closest edges of central portions of the adjacent two of the first active areas;
at least a column of second active areas, the second active areas extending along the first direction, each of the second active areas comprising: a second channel region, a third source/drain region and a fourth source/drain region disposed on two sides of the second channel region, and a second programming region, the second programming region being disposed at an end portion of a given one of the second active areas, wherein an end portion, closest to the first active areas, of the given second active area directly faces a region between end portions, closest to the given second active area, of two adjacent first active areas;
a first gate line, the first gate line covering each of the first channel regions in a given column of the first active areas;
a second gate line, the second gate line covering each of the second channel regions in a given column of the second active areas; and
a programming gate line, the programming gate line covering each of the first programming regions in the given column of the first active areas, and the programming gate line further covering each of the second programming regions in the given column of the second active areas.