US 12,471,273 B2
Semiconductor memory device
Eunjung Kim, Daegu (KR); Hyunyong Kim, Daegu (KR); Sangho Lee, Suwon-si (KR); Yongseok Ahn, Seoul (KR); and Jay-Bok Choi, Yongin-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Apr. 26, 2022, as Appl. No. 17/729,024.
Claims priority of application No. 10-2021-0080853 (KR), filed on Jun. 22, 2021.
Prior Publication US 2022/0406791 A1, Dec. 22, 2022
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/485 (2023.02) [H10B 12/482 (2023.02); H10B 12/488 (2023.02)] 15 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
a device isolation pattern in a substrate and defining a first active section and a second active section that are spaced apart from each other, a center of the first active section being adjacent to an end of the second active section;
a bit line that crosses over the center of the first active section;
a bit-line contact between the bit line and the first active section; and
a first storage node pad on the end of the second active section,
wherein the first storage node pad contacts an upper surface, a first sidewall, and a second sidewall of the second active section,
wherein the first storage node pad includes a first pad sidewall and a second pad sidewall, the first pad sidewall being adjacent to the bit-line contact, and the second pad sidewall being opposite to the first pad sidewall,
wherein, when viewed in plan, the second pad sidewall is convex in a direction away from the bit-line contact, and
wherein the first active section and the second active section extend above the upper surface of the device isolation pattern.