| CPC H10B 12/315 (2023.02) [H10B 12/0335 (2023.02); H10B 12/34 (2023.02); H10B 12/482 (2023.02)] | 20 Claims |
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1. A DRAM, comprising:
a plurality of buried word line structures in a substrate;
a plurality of bit line stack patterns on the substrate; and
a plurality of spacers, located on sidewalls of the plurality of bit line stack patterns, wherein each of the spacers comprises:
a first dielectric layer, disposed on the sidewalls of the bit line stack pattern;
a second dielectric layer, disposed on a sidewall of the first dielectric layer; and
a third dielectric layer, disposed on a sidewall of the second dielectric layer, wherein a top surface of the second dielectric layer is lower than a top surface of the first dielectric layer and a top surface of the third dielectric layer; and
a fourth dielectric layer, disposed on the top surface of the second dielectric layer,
wherein the second dielectric layer and the fourth dielectric layer are disposed between the first dielectric layer and the third dielectric layer, and the second dielectric layer is made of a dielectric material of which a dielectric constant is lower than that of the first dielectric layer, the third dielectric layer, and the fourth dielectric layer;
a plurality of capacitor contacts, electrically connected to active regions in the substrate, wherein top surfaces of the plurality of capacitor contacts are lower than the top surface of the second dielectric layer; and
a plurality of capacitor landing pads, covering the plurality of capacitor contacts, first portions of the plurality of spacers, and a portion of the plurality of bit line stack patterns, wherein top surfaces of second portions of the plurality of spacers not covered by the plurality of capacitor landing pads are lower than top surfaces of the first portions of the plurality of spacers.
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