| CPC H10B 12/315 (2023.02) | 20 Claims |
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1. A semiconductor device, comprising:
a substrate including an active region;
a word line structure crossing the active region and extending in a first horizontal direction parallel to a top surface of the substrate;
a bit line structure extending in a second horizontal direction on the substrate, the second horizontal direction being parallel to the top surface of the substrate and intersecting the first horizontal direction;
a bit line contact electrically connecting a first impurity region of the active region to the bit line structure;
a storage node contact on a sidewall of the bit line structure and electrically connected to a second impurity region of the active region; and
a contact barrier layer covering at least a portion of the bit line contact,
wherein:
the bit line contact includes a lower portion having a first width in the first horizontal direction and an upper portion on the lower portion and having a second width in the first horizontal direction,
the first width is greater than the second width, and
the contact barrier layer covers a bottom surface and a side surface of the lower portion, and
wherein the contact barrier layer is disposed in a space between the bottom surface of the lower portion of the bit line contact and an upper surface of the first impurity region of the active region in a vertical direction perpendicular to the top surface of the substrate.
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