US 12,471,267 B2
Transistor and manufacturing method thereof, and memory
Youming Liu, Hefei (CN); and Deyuan Xiao, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jul. 29, 2022, as Appl. No. 17/816,156.
Application 17/816,156 is a continuation of application No. PCT/CN2022/098249, filed on Jun. 10, 2022.
Claims priority of application No. 202210608341.1 (CN), filed on May 31, 2022.
Prior Publication US 2023/0389276 A1, Nov. 30, 2023
Int. Cl. H10D 30/67 (2025.01); H10B 12/00 (2023.01)
CPC H10B 12/30 (2023.02) [H10B 12/05 (2023.02)] 10 Claims
OG exemplary drawing
 
1. A transistor, comprising:
a channel, wherein the channel itself encloses an accommodation space;
a gate, provided with a first end and a second end that are opposite, wherein the first end of the gate is located inside the accommodation space, and the second end of the gate is located outside the accommodation space;
a dielectric layer, located between the gate and the channel, insulating and isolating the gate and the channel;
a source, provided at one end of the channel; and
a drain, provided at the other end of the channel, wherein the drain and the source are arranged at intervals along a length direction of the channel, and
the source, the drain, and the channel are each made of a semiconductor material.