US 12,471,215 B2
Printed circuit board with reduced via striping
Sandor Farkas, Round Rock, TX (US); and Bhyrav Mutnury, Austin, TX (US)
Assigned to Dell Products L.P., Round Rock, TX (US)
Filed by DELL PRODUCTS L.P., Round Rock, TX (US)
Filed on Jul. 30, 2023, as Appl. No. 18/361,854.
Prior Publication US 2025/0040045 A1, Jan. 30, 2025
Int. Cl. H05K 1/11 (2006.01); H05K 1/02 (2006.01); H05K 3/00 (2006.01); H05K 3/42 (2006.01)
CPC H05K 1/115 (2013.01) [H05K 1/0298 (2013.01); H05K 3/0047 (2013.01); H05K 3/429 (2013.01); H05K 2201/096 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A printed circuit board comprising:
a dielectric material;
a signal trace on a surface of the dielectric material;
a signal layer within the dielectric material;
a via including plating, the plating providing an electrical communication between the signal trace and the signal layer, wherein the via has a diameter; and
a plurality of back drill locations along a length of the via beyond the signal layer, wherein a first combined diameter of the back drill locations at a bottom of the back drill locations is equal to the dimeter of the via, and wherein a second combined diameter of the back drill locations at a top of the back drill locations is greater than the dimeter of the via, wherein the back drill locations include first, second, and third back drill locations.