| CPC H04W 72/02 (2013.01) [H04L 5/0053 (2013.01); H04W 72/0446 (2013.01); H04W 72/0453 (2013.01); H04W 72/20 (2023.01); H04W 72/23 (2023.01)] | 18 Claims |

|
1. A baseband processor configured to cause a wireless device to:
receive control information through a sidelink control channel, wherein the control information specifies a plurality of first time slots for the wireless device to transmit a sidelink acknowledgment message over a sidelink feedback channel, wherein the sidelink acknowledgment message is related to a sidelink data packet received by the wireless device;
receive a resource grant through a downlink control channel, wherein the resource grant specifies one or more second time slots for the wireless device to transmit an uplink transmission over an uplink channel;
determine that one or more of the first time slots comprise overlapping time slots that coincide with one or more of the second time slots;
determine whether the sidelink data packet and the uplink transmission differ in priority by more than a predetermined threshold amount,
based at least in part on a determination that the sidelink data packet and the uplink transmission differ in priority by more than the predetermined threshold amount, transmit the sidelink acknowledgment message over the sidelink feedback channel or transmit the uplink transmission over the uplink channel during the overlapping time slots; and
based at least in part on a determination that the sidelink data packet and the uplink transmission differ in priority by less than the predetermined threshold amount or have a same priority, transmit the sidelink acknowledgment message over the sidelink feedback channel during a first subset of the overlapping time slots and transmit the uplink transmission over the uplink channel during a second subset of the overlapping time slots separate from the first subset.
|