US 12,470,851 B2
Distributed ramp linearity compensation circuit
Hiroaki Ebihara, San Jose, CA (US); Nobuhiro Yanagisawa, San Jose, CA (US); Satoshi Sakurai, Cupertino, CA (US); Tomoyasu Tate, Cupertino, CA (US); Naoki Kitazawa, Yokohama (JP); and Kohei Harada, Yokohama (JP)
Assigned to OMNIVISION TECHNOLOGIES, INC., Santa Clara, CA (US)
Filed by OMNIVISION TECHNOLOGIES, INC., Santa Clara, CA (US)
Filed on Aug. 1, 2023, as Appl. No. 18/363,469.
Prior Publication US 2025/0048002 A1, Feb. 6, 2025
Int. Cl. H04N 25/78 (2023.01); H04N 25/709 (2023.01); H04N 25/76 (2023.01)
CPC H04N 25/78 (2023.01) [H04N 25/709 (2023.01); H04N 25/7795 (2023.01)] 20 Claims
OG exemplary drawing
 
1. An imaging system, comprising:
a pixel array configured to generate a plurality of image charge voltage signals in response to incident light; and
readout circuitry coupled to the pixel array, the readout circuitry including a plurality of column unit cells, wherein each column unit cell comprises:
at least one of a plurality of comparators, wherein each comparator is coupled to receive a corresponding one of the image charge voltage signals from the pixel array, compare the corresponding one of the image charge voltage signals to a ramp signal from a ramp generator, and provide a digital representation of the corresponding one of the image charge voltage signals in response, and wherein each comparator is coupled to receive the ramp signal from the ramp generator through a ramp signal line; and
a compensation current unit coupled to the ramp signal line, comprising:
a compensation current source; and
a compensation current switch coupled to the compensation current source,
wherein the compensation current source and the compensation current switch are coupled between a first node on the ramp signal line and a second node.