	US 12,470,748 B2
	Methods and apparatus to identify a video decoding error
Jill Boyce, Portland, OR (US); and Basel Salahieh, Santa Clara, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Appl. No. 17/915,431
Filed by Intel Corporation, Santa Clara, CA (US)
PCT Filed Dec. 11, 2020, PCT No. PCT/US2020/064438 § 371(c)(1), (2) Date Sep. 28, 2022, PCT Pub. No. WO2021/201928, PCT Pub. Date Oct. 7, 2021.
Claims priority of provisional application 63/004,741, filed on Apr. 3, 2020.
Prior Publication US 2023/0239508 A1, Jul. 27, 2023
Int. Cl. H04N 19/65 (2014.01); H04N 19/597 (2014.01)

CPC H04N 19/65 (2014.11) [H04N 19/597 (2014.11)]

25 Claims

1. A video encoding apparatus comprising:

interface circuitry to obtain input views of video;

computer readable instructions; and

at least one processor circuit to be programmed by the computer readable instructions to at least:

generate mapping data that maps blocks in one or more atlases to patches, the one or more atlases generated from one or more of the input views of video;

perform a hash operation on the mapping data to generate a hash value;

include the hash value in a message; and

combine the one or more atlases and the message to generate a video bitstream.